Session 1: Registration & opening
Chairs: Eugenio Villar and Frédéric Pétrot
Chair: Eugenio Villar
Abstract: In this talk we’ll discuss the semiconductor industry focusing on its fabless component and analyze it from a European perspective. A brief discussion on the different players within the semiconductor industry will be followed by thoughts and remarks on the current status of the fabless and foundry ecosystem in Europe
Session 3A: Hardware and Software for RISC-V
Chairs: Francesc Moll and Borja Pérez
11:00 Sara Alonso, Alejandro Arteaga, Leire Muguira, Carlos Cuadrado, Aitzol Zuloaga, Jaime Jiménez, Jesús Lázaro, José Ignacio Gárate, José Angel Araujo, Victor Martínez, Unai Bidarte and Armando Astarloa
A proof-of-concept ASIC RISC-V based SoC for Industrial Applications (abstract)
11:30 David Cantero, Alex Ugena, Laura Sanz, Alejandro Arteaga and Armando Astarloa
Performance Analysis of Convolution Function for IA Edge Computing Acceleration using a 32-bit RISC-V CPU Implementation (abstract)
12:00 Roman Cardenas, Pedro Malagon, Patricia Arroba, Josue Pagan and Jose M. Moya
RISCV-SLIC: Rust Software Level Interrupt Controller for RISCV microcontrollers (abstract)
Session 3B: Sensing
Chairs: Armando Astarloa and Yolanda Lechuga
11:00 Andrea Sannino, José Ignacio Artigas and Aránzazu Otín
An Improved Discrete Time Amplifier-Less Potentiostat Architecture for Metabolic Sensing Applications (abstract)
11:30 Michel Justino Bai, Iñigo Adin Marcos and Markos Losada Gobantes
Learning to Sense Sustainably: RL-Based Control for Solar-Powered IoT Nodes (abstract)
12:00 Abel Reyes Cubas, David Galante Sempere and Javier Del Pino Suárez
A built-in CMOS temperature sensor for On-Chip Thermal Monitoring from 0ºC to 100ºC with a 0.137ºC of Innacuracy (abstract)
Session 4A: Security and Power Systems
Chairs: Jorge Portilla and Luis Parrilla
12:30 Sergio Tejeda Campos, Roberto Román, Rosario Arjona and Iluminada Baturone
Electromagnetic Side-Channel Attack on a Cloud-Based Fingerprint Recognition System (abstract)
13:00 Erica Tena-Sánchez, Francisco Eugenio Potestad Ordóñez, Miguel Martín-González, Alejandro Casado-Galán and Antonio J. Acosta
Low Entropy Masking Protection Scheme for ASCON Cipher to Counteract Side-Channel Attacks (abstract)
13:15 Carlos Fernández-García, Carlos J Jiménez-Fernández, Pilar Parra Fernández and Carmen Baena Oliva
A Lightweight AES Peripheral for RISC-V Cores and IoT Applications (abstract)
13:45 Pilar Cano-Lozano, Enrique Personal, Diego Francisco Larios, Samuel Dominguez-Cid, Juan Ignacio Guerrero and Carlos León
Electric vehicle emulator for study as a Distributed Energy Resource (abstract)
Session 4B: Signal Processing and Power Systems
Chairs: José Machado Da Silva and Luis Entrena
12:30 Santiago Murano, Martin Alejandro Colombo, Carlos De Marziani, Rubén Nieto Capuchino and Sofia Micaela Laskowski Orlandi
FPGA Architectures for Reliable Transmission of Pre-Stored Acoustic Signals in Underwater Localization Systems (abstract)
13:00 Fermin Esparza and Antonio Lopez-Martin
CMOS Micropower Current-Mode Sinh-Domain Filter with Multidecade Tuning (abstract)
13:30 Óliver P. Westin, Rafael T. Inuoe, Anderson A. Dionizio, Leonardo P. Sampaio and Sérgio A. Oliveira da Silva
Improved Modified Zeta Inverter for Single-Phase Grid-Tied System (abstract)
Session 5A: AI Circuits and Systems
Chairs: Juan Carlos López and Fernando Herrera
15:30 Marina Cordovilla Serrano, Pablo Sánchez Espeso and Andrés Martínez Lozano
Efficient Neural Architectures for Acoustic Monitoring of Livestock (abstract)
16:00 Rubén Padial-Allué, Alberto Martín-Martín, Encarnación Castillo, Uwe Meyer-Baese, Víctor Toral, Luis Parrilla and Antonio García
1-D Convolutional Autoencoder for Fetal and Maternal ECG Classification Oriented to Hardware Implementation Acceleration (abstract)
16:30 Jordi Fornt, Pau Fontova-Musté, Martí Caro, Jaume Abella, Josep Altet, Antonio Rubio and Francesc Moll
Approximate Circuits versus Quantization for Energy Efficient Deep Neural Networks (abstract)
Session 5B: Neuromorphic Circuits, Systems and Technologies I
Chair: Koldo Basterretxea and Antonio Rubio
15:30 Josep L. Rosselló, Christian F. Frasser, Arnau Salas-Barenys, Joan Cesari, Vincent Canals, Lluc Crespí-Castañer, Joan Font-Rosselló, Alejandro Morán Costoya and Miquel Roca
A 1.12 TOPS/W 180nm Stochastic Computing-based Neuromorphic Circuit (abstract)
16:00 Alejandro Morán, Lluc Lluc Crespí-Castañer, Christiam F. Franco, Joan Font-Rosselló, Vincent Canals, Miquel Roca and Josep L. Rosselló
A Comparative Analysis of Bipolar and Sign-Magnitude Stochastic Computing Approaches in Quantized Neural Networks (abstract)
16:30 Didac Llobet, Ioannis Chatzipaschalis, Antonio Calomarde and Antonio Rubio
Character Recognition Application of a Neural Circuit Including Lateral Inhibitory Mechanisms (abstract)
Session 6A: Neuromorphic Circuits, Systems and Technologies II
Chairs: Roberto Sarmiento and Hector Posadas
17:00 Prathamesh Satish Deshpande, Giovanni Grandi, Stephan Schoenfeldt and Fabian Lurz
Full-Integer Spiking Neural Network Inference with RISC-V ISA Extensions for Radar-based Gesture Recognition (abstract)
17:30 Bernabe Linares-Barranco, Luis Alejandro Camuñas Mesa and Teresa Serrano-Gotarredona
Three decades of IMSE Neuromorphic Engineering Group (abstract)
18:00 Cristina Bermúdez Martín, Samuel López Asunción and Pablo Ituero
Design Space Exploration of FPGA-Based Spiking Neural Networks for Angle of Arrival Detection (abstract)
Session 6B: System-Level Analysis and Exploration
Chair: Antonio Rubio and Koldo Basterretxea
17:00 Markel Galarraga, Charles-Alexis Lefebvre, Jon Perez-Cerrolaza and Jose A. Pascual
Analyzing Linux System Call Variability: Real-Time Patch Impact and System Call Monitoring (abstract)
17:30 Jose Luis Mira Serrano, Carlos Ernesto Hernandez Orellana, Jesús Barba Romero, María Soledad Escolar Diaz, Jose Antonio de la Torre Las Heras and Fernando Rincon Calle
Exploring Design Spaces in Embedded Systems: An Approach Based on Genetic Programming, Particle Swarm and Reinforcement Learning (abstract)
18:00 Eduardo Tomasi, César Fuguet, Christian Fabre and Frédéric Pétrot
HPC Workload Analysis Using Distributed Cross-ISA Binary Instrumentation (abstract)
Chair: Francisco Fernandez
Abstract: In the recent years, AI algorithms became so accurate that started to surpass human being in a wide range of tasks and are now currently used in applications that would be considered science-fiction only 10 years ago. However, everything as a cost and, for AI, it corresponds to the tremendous requirements in terms of computational power that driven the development of specialized hardware architectures (i.e., hardware accelerator) for DL workloads. One of the most popular hard- ware accelerator is the Systolic Array (SA) architecture, which is suitable to run inferences with low energy, low latency and high throughput. In particular, there exists virtually infinite types of SA in terms of dataflow depending on the kernel they have to run. If from one hand SA dataflow has been widely studied to improve energy efficiency and performance, the impact on the resilience to hardware faults has been neglected. Hardware faults can indeed jeopardize the execution of DL kernels leading to miss- classification and eventually to dramatic impacts when DL are used in safety-critical applications, such as autonomous driving. This talk will discusses the main consequences on the choice of a given hardware architecture to achieve by design Trustworthiness.
Session 9A: AI-Driven Development of High-Performance Electronic Systems and Applications-1
Chairs: Pablo Sanchez and Jesús Barba
11:00 Daniel Suárez, Pedro Hernández, Víctor Fernández and Gustavo Marrero
Video Action Recognition in SoC FPGAs driven by Neural Architectural Search (abstract)
11:30 Jaime Sancho, Manuel Villa, Gonzalo Rosa-Olmeda, Alejandro Martínez de Ternero, Miguel Chavarrías, Eduardo Juárez and César Sanz
Deep Learning-Based Depth Estimation for Facial Morphology Characterization in Neurosurgery Applications (abstract)
12:00 Félix David Suárez Bonilla, Gustavo Liñán-Cembrano and José Manuel De la Rosa Utrera
Multi-Domain Feature Extraction for ML-Based Over-the-Air RF Signal Classification (abstract)
Session 9B: Monitoring and Control
Chairs: María J. Avedillo and Francisco Fernandez
11:00 Rafaella Fiorelli, Juan Núñez Martínez and Eduardo Peralías
Nano-Oscillator Output Signal Monitoring Technique: Method and Device Implementation (abstract)
11:30 Amadeo de Gracia Herranz, Borja Gutierrez de Cabiedes, Javier de Mena Pacheco and Marisa Lopez-Vallejo
Ultra-Narrow Current Pulses Measurement Using a Cost-Effective Instrumentation System (abstract)
11:45 Juan Luis Soler-Fernandez, Angel Diéguez, Joan Daniel Prades and Oscar Alonso
Sub-nW Thyristor Based Wake-Up Timer for Low Duty Cycle IoT Sensing Applications (abstract)
12:15 Chih-Feng Wu, Bo-An Lin and Chi-Tien Sun
A 4×4 K-best Spatial Modulation MIMO Detection for Visible Light Communication Systems (abstract)
Session 10A: Circuit Design and Analysis
Chairs: Antonio Torralba and Miquel Roca
12:30 Juan Núñez, Rafaella Fiorelli and María J. Avedillo
Digital Ising-Based Solver for Scalable Max-Cut Optimization (abstract)
13:00 Muhammad Umer Khalid, Trond Ytterdal and Snorre Aunet
Comparative Analysis of Full Adders based on DTMOS Schmitt-Trigger Standard Cells Operating at Sub-100 mV Supply Voltage (abstract)
13:30 José Manuel Cruz Acosta, Irene Merino-Fernández, Javier del Pino and Sunil L. Khemchandani
Machine Learning-Based Physical Design of RFIC Transformers (abstract)
Session 10B: Powering circuits
Chairs: Alfio Dario Grasso and Aranzazu Otin
12:30 Mukul Agarwal, Nikhil Chourasiya, Sai Sumanth Pothuri and Subodh Prakash Taigor
Novel methodology for optimization of Charge Pump efficiency (abstract)
13:00 Mehdi Shahabi, Andoni Beriain Rodríguez and Noemi Perez Hernandez
A 65nm CMOS Ultra-Low-Quiescent-Current On-Chip PMIC for Energy-Limited Harvesting Systems (abstract)
13:30 Maria Clara Simões, Floriberto Lima, Marcelino Santos and Fábio Passos
A 300mA Fully-Integrated Inverter-Based LDO with Enhanced Supply Insensitivity for Smart Edge AI Applications (abstract)
Session 11: Industry-University Collaboration and Technology Transfer
In this panel, the MicroNanoSpain Competence center will be presented. Then, the panelists will presents their points of view about industry-university cooperation opportunities in electronic and microelectronic research and training:
- Alfonso Gabarron, AESEMI & MicroNanoSpain Competence Center
- Ana Peláez, Maxwell
- Eduardo Casanueva, INDRA
- Constantino Ruiz, AWGE
Chair: Antonio Lopez-Martin
Chair: Roc Berenguer
Abstract: Non-volatile memory (NVM) has played a pivotal role in the advancement of embedded systems, enabling persistent data storage across a wide spectrum of applications. The journey began with the development of electrically erasable programmable read-only memory (EEPROM) and multi-time programmable (MTP) technologies, which laid the foundation for reliable, low-power memory solutions in constrained environments. These early NVM architectures offered modest density and endurance but were instrumental in enabling secure data retention in analog and mixed-signal systems.
The emergence of Flash memory marked a significant leap in NVM capabilities, introducing higher density, faster access times, and scalable architectures suitable for both standalone and embedded applications. Flash variants became ubiquitous across consumer electronics, automotive systems, and industrial platforms. However, as process nodes scaled down and system requirements evolved, traditional Flash technologies began to encounter limitations in terms of write endurance, retention, and integration complexity—especially in ultra-low power and cost-sensitive domains.
This keynote provides a comprehensive overview of the current NVM landscape, with a particular emphasis on technologies derived from the MTP and Flash lineage applied to RFID (Radio-Frequency Identification) systems. We examine the trade-offs between endurance, retention, power consumption, and die area, and how these factors influence the selection of NVM in embedded designs.
In RFID (Radio-Frequency Identification) systems, where memory performance is tightly coupled with tag functionality, cost, and energy efficiency. RFID tags—especially passive and semi-passive types—demand memory solutions that operate reliably under stringent power and environmental constraints. EEPROM and MTP-based NVMs remain dominant in this space due to their proven reliability, low-voltage operation, and compatibility with analog front-end circuitry.
We analyze the specific memory requirements of RFID ICs, including write cycle limitations, retention across temperature extremes, and the need for secure data storage in authentication and anti-counterfeiting applications. The integration of NVM into RFID chips presents unique challenges, such as minimizing silicon footprint, ensuring process compatibility, and achieving cost targets for high-volume deployment.
The paper concludes with a discussion on future directions in NVM development for RFID and other embedded applications. Topics include the refinement of Flash and MTP architectures, and innovations in low-voltage programming techniques. As RFID continues to expand into new domains—from supply chain logistics to healthcare and smart packaging—the role of optimized NVM will be increasingly critical in enabling secure, efficient, and scalable solutions.
Session 14A: Hardware Accelerators
Chairs: Javier Uceda and Jaime Jiménez
11:00 Francisco Albertuz and Mario Garrido
Hardware-Efficient Gaussian and Sobel Filters for Real-Time Image Processing on FPGA (abstract)
11:30 Lluís Ribas-Xirgo
Hardware implementation of the Hungarian algorithm for optimum task assignments (abstract)
12:00 Pablo Hormigo-Jimenez and Javier Hormigo
Configurable Ultra-High-Throughput QRD FPGA Accelerators for small matrices (abstract)
12:15 Rubén Nieto, Silvia Iniesta, Santiago Murano, Pedro R. Fernández and Susana Borromeo
FPGA-Based Implementation of sEMG Feature Extraction and Movement Classification with MLP (abstract)
Session 14B: RF & Communications
Chairs: Roc Berenguer and Jose Ángel Miguel Díaz
11:00 Uxua Esteban-Eraso, Gesler Ramos, Santiago Celma, Francisco José Torcal-Milla and Carlos Sanchez-Azqueta
Design of a CMOS Transmitter Chain for Satellite on the Move Communications (abstract)
11:30 Alvaro Urain, David Del Rio, Andoni Beriain, Hector Solar, Roc Berenguer and Aleksei Nerushenko
Design of a 160-210 GHz SiGe HBT Square-Law Detector for Total Power Radiometers (abstract)
12:00 F. Bonfiglio-Buendía, Natalia-Abel Fernández-García, P. López, Victor M. Brea and Diego Cabello
CMOS SPDT Switch Topologies in the Frequency Range of 6 to 20 GHz (abstract)
Session 15A: AI-Driven Development of High-Performance Electronic Systems and Applications-2
Chairs: Pablo Sanchez and Soledad Escolar
12:30 Juan Gallego, José Ferreira, Luís Alves, Daniel Vázquez, João Bispo, Alfonso Rodríguez, Nuno Paulino and Andrés Otero
Acceleration of C/C++ Kernels and ONNX Models on CGRAs with MLIR-Based Compilation (abstract)
13:00 Maryam Katebzadeh, Daniel Vaquez, Andres Otero and Alfonso Rodriguez
A Framework for Automated CGRA Design Space Exploration with Genetic Algorithm Optimization (abstract)
13:30 Irene Merino-Fernandez, José Manuel Cruz Acosta, Javier del Pino and Sunil L. Khemchandani
Machine Learning for Microwave Pixelated Structures Design (abstract)
Session 15B: Quantum and low power
Chairs: Eduard Alarcon and Jose Maria Lopez Villegas
12:30 Aleksei Nerushenko, Hector Solar, Roc Berenguer and Alvaro Urain
A 1.15 mW SiGe BiCMOS Cryogenic LNA for Superconducting Qubit Readout with 4.5 K Noise Temperature from 4 to 9 GHz (abstract)
13:00 Ainhoa Leal, Luis Montal, Aleksei Nerushenko, Hector Solar and Roc Berenguer
A Methodology for Cryogenic Modeling of CMOS Technology Based on BSIM-BULK (abstract)
13:15 Muhammad Umer Khalid, Trond Ytterdal and Snorre Aunet
Robust DTMOS Schmitt-Trigger Circuits in 130 nm SOI CMOS for Sub-100 mV Supply Voltage (abstract)
13:45 Tom Bergmann, Joel Damiens, Alfonso Hildebrand Rueda, Stephane Lacouture, Remy Cellier and Nacer Abouchi
A Programmable, Negative, and Dynamically Biased Sampler for Ultra-Low Power Body-Bias Generators in 18nm FD-SOI (abstract)
Juan Manuel Galan Serrano (CEIT-Basque Research and Technology Alliance (BRTA)), Javier Alonso Tirapu (CEIT-Basque Research and Technology Alliance (BRTA)), Andoni Irizar Picon (CEIT-Basque Research and Technology Alliance (BRTA)) and Ainhoa Cortes Vidal (CEIT-Basque Research and Technology Alliance (BRTA)).
VEC32-V: A versatile, extendible and configurable 32b RISC-V based MCU.
Wael Elmanhawy (Product Management Director) and Pranit Oza (Product Engineer).
Automated SPICE Consolidation for Faster Circuit Verification.
Sara Portero (ICCUB – University of Barcelona), David Mazzanti (ICCUB – University of Barcelona), Juan José Silva (ICCUB – University of Barcelona), Jose Maria Fernandez (ICCUB – University of Barcelona) and David Gascón (ICCUB – University of Barcelona).
Front End Readout Solutions for TOF-PET systems employing analog SiPMs.
José Angel Flores Bravo (UPV/EHU), Armando Astarloa (UPV/EHU), Jesús Lázaro (UPV/EHU), Aitzol Zuloaga (UPV/EHU) and Carlos Cuadrado (UPV/EHU).
Applications of Multipoint Distributed Fiber Optic Sensors for Monitoring in Critical Systems.
Kerman Pérez (UPV/EHU), Alejandro Arteaga (UPV/EHU), Jaime Jiménez (UPV/EHU), Armando Astarloa (UPV/EHU) and Jesús Lázaro (UPV/EHU).
Enriching Spacewire Virtual Testbeds with Python-based Simulation Tools.
Hasnain Raza (University of Granada), Luis Parrilla (University of Granada), Encarnacion Castillo (University of Granada), Ruben Padial (UGR) and Antonio García (University of Granada).
Area-Efficient Point-Wise Multiplication for Crystals-Kyber.
Francisco Eugenio Potestad-Ordóñez (Escuela Politécnica Superior/Instituto de Microelectrónica de Sevilla (IMSE-CNM-CSIC-US)), Miguel Martín-González (Instituto de Microelectrónica de Sevilla (IMSE-CNM-CSIC-US)), Alejandro Casado-Galán (Instituto de Microelectrónica de Sevilla (IMSE-CNM-CSIC-US)) and Erica Tena-Sánchez (Escuela Politécnica Superior/Instituto de Microelectrónica de Sevilla (IMSE-CNM-CSIC-US)).
Error Detection and Correction Hardware Protection for ASCON cipher against fault analysis attacks.
Matheus Minelli de Carvalho (IMT, Telecom Paris, LTCI, Institut Polytechnique de Paris), Benjamin Cheymol (CNRS, IN2P3, LPSC, Univ. Grenoble Alpes), Lirida Naviner (IMT, Telecom Paris, LTCI, Institut Polytechnique de Paris) and Rodrigo Possamai Bastos (CNRS, Grenoble INP, TIMA, Univ. Grenoble Alpes).
Near-sensor testing method for observing radiation-induced soft errors in modern sensors.
Zeyuan Hui (Universitat Autònoma de Barcelona), Ivan Zamora (Universitat Autònoma de Barcelona), Arantxa Uranga (Universitat Autònoma de Barcelona) and Nuria Barniol (Universitat Autònoma de Barcelona).
Design of an Element-Level Delay Line with Duty-Cycle Correction for a large PMUT Array.
Álvaro Falcón Santana (Universidad de Las Palmas de Gran Canaria), Carlos Vega García (Universidad de Las Palmas de Gran Canaria), Antonio José Rodríguez Almeida (Universidad de Las Palmas de Gran Canaria), Himar Fabelo Gómez (Universidad de Las Palmas de Gran Canaria), Pedro Francisco Pérez Carballo (Universidad de Las Palmas de Gran Canaria) and Gustavo Iván Marrero Callicó (Universidad de Las Palmas de Gran Canaria).
MRI segmentation and mesh generation targeting real-time brain-shift compensation in neurosurgery.
Lydia Bush-Espinosa (IC Málaga), Michael Gater (University of Nottingham), Carol de Benito (Universitat Illes balears), Stavros Stavrinides (Democritus University of Thrace), Miquel Roca (University of Balearic Islands), Salvador Dueñas (UNIVERSIDAD DE VALLADOLID), Álvaro Pineda (IC Málaga) and Rodrigo Picos (Universitat de les Illes Balears).
A programming system using current pulses for organic memristors deposited on the same chip.
Amalia Arias (IMB-CNM (CSIC)), Manuel Lozano (IMB-CNM (CSIC)), Esteve Amat (IMB-CNM (CSIC)), Alvaro Pineda (Integrated Circuits Malaga S.L.), Bartomeu Servera (Integrated Circuits Malaga S.L.) and Angel Barbancho (Integrated Circuits Malaga S.L.).
Floating-Gate Based Hybrid Sensor for Low-Power CMOS-Compatible Radiation Dosimetry.
Alfonso Guerrero-de-Mier (University of Seville), Pedro Blanco-Carmona (University of Seville), Ramón González-Carvajal (University of Seville) and Alejandro Rodríguez-González (Guadalquivir Hydrographic Confederation).
A Methodological Framework for Developing Digital Twins in River Basins.
Emili Manzano-Aguilar (University of the Balearic Islands), Bartomeu Alorda-Ladaria (University of the Balearic Islands), Carola De Benito (University of the Balearic Islands), Francisco J. Cereceda (University of the Balearic Islands) and Jesus Molina (University of the Balearic Islands).
Non-Invasive Data Extraction OCR based method for Commercial Medical Devices.
Joan Teruel (Barcelona Supercomputing Center / Universitat Politecnica de Catalunya), Elias Perdomo (Barcelona Supercomputing Center / Universitat Politecnica de Catalunya), David Castells (Barcelona Supercomputing Center / Universitat Autònoma de Barcelona), Xavier Martorell (Barcelona Supercomputing Center / Universitat Politecnica de Catalunya) and Behzad Salami (Barcelona Supercomputing Center).
Telemetry Tools for Alveo Accelerator Cards.
